Encoding:

Format:

ADDQH[_R].PH 

ADDQH.PH     rd, rs, rt

ADDQH_R.PH   rd, rs, rt

Purpose:

Add Fractional Halfword Vectors And Shift Right to Halve Results

Element-wise fractional addition of halfword vectors, with a right shift by one bit to halve each result, with optional rounding.

Description:

rd = round((rs31..16 + rt31..16) >> 1) || round((rs15..0 + rt15..0) >> 1)

Each element from the two halfword values in register rs is added to the corresponding halfword element in register rt to create an interim 17-bit result.

In the non-rounding instruction variant, each interim result is then shifted right by one bit before being written to the corresponding halfword element of destination register rd.

In the rounding version of the instruction, a v alue of 1 is added at the least-significant bit position of each interim result; the interim result is then right-shifted by one bit and written to the destination register.

This instruction does not modify the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDQH.PH
   ValidateAccessToDSP2Resources()
   tempB15..0 = rightShift1AddQ16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = rightShift1AddQ16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]31..0 = tempB15..0 || tempA15..0
ADDQH_R.PH
   ValidateAccessToDSP2Resources()
   tempB15..0 = roundRightShift1AddQ16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = roundRightShift1AddQ16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]31..0 = tempB15..0 || tempA15..0
function rightShift1AddQ16( a15..0 , b15..0 )
   temp16..0 = (( a15 || a15..0 ) + ( b15 || b15..0 ))
   return temp16..1
endfunction rightShift1AddQ16
function roundRightShift1AddQ16( a15..0 , b15..0 )
   temp16..0 = (( a15 || a15..0 ) + ( b15 || b15..0 ))
   return temp16..1
endfunction roundRightShift1AddQ16

Exceptions:

Reserved Instruction, DSP Disabled